Minimum instruction execution time: 31.25 ns (at 32 MHz operation)
30.5 μs (with subclock (fXT) = 32.768 kHz operation)
Memory space Program (physical address) space: 64 MB linear
Data (logical address) space: 4 GB linear
General-purpose registers: 32 bits × 32 registers
Internal 32-bit architecture
5-stage pipeline control
Multiplication/division instruction
Saturation operation instruction
32-bit shift instruction: 1 clock
Load/store instruction with long/short format
Four types of bit manipulation instructions
UPD70F3373,UPD70F3558,UPD70F3747, UPD70F3750,
UPD70F3752, UPD70F3755,UPD70F3757,UPD70F3797, UPD70F3798,
UPD70F3799, UPD70F3800,UPD70F3801,UPD70F3802, UPD70F3803,
UPD70F3804, UPD70F3805,UPD70F3806,UPD70F3807, UPD70F3808,
UPD70F3735, UPD70F3736,UPD70F3739,UPD70F3740, UPD70F3741,
UPD70F3742, UPD70F3737,UPD70F3738,UPD70F3792, UPD70F3793,
UPD70F3743, UPD70F3744,UPD70F3745,UPD70F3746, UPD70F3107